1. Technical Field
The embodiments herein generally relate to a vector slot processor, and, more particularly, to a vector slot processor that is capable of performing multiple signal processing operations of finite impulse response filters, decimators, interpolators and cubic polynomial based waveform interpolations for high speed streaming inputs.
2. Description of the Related Art
In digital communication systems, it is essential to convert an incoming intermediate frequency (IF) signal to a baseband signal before further processing. In addition, the baseband signal needs to be filtered before processing any symbol. This is very computationally intensive, especially if the incoming stream of samples is at a high speed. Current application specific hardwired architectures typically support single or very few demodulation standards. This becomes extremely challenging for a software defined radio (SDR) platform that supports multiple demodulation standards. Typical digital signal processing (DSP) CPUs do not provide an optimized and scalable solution that caters to all data rates.
A demodulation chain of any digital communication receiver typically includes a first section where the intermediate frequency (IF) signal is digitized after receiving it from a tuner using an analog to digital convertor (ADC). This digitized signal can be optionally converted to baseband. When there is a need to cater to a specific demodulation receiver, the design features are supported which is optimized for a combination of sample rates (as obtained from ADC) and required symbol rates. Such design features are inflexible and not scalable for higher sampling rates or multiple input streams as is the case for multiple-input and multiple-output (MIMO) communication systems.